1. Technical Field
Various embodiments of the present invention relates to a semiconductor memory apparatuses and related methods. In particular, certain embodiments relate to a three-dimensional (3D) semiconductor apparatus in which a plurality of chips are stacked.
2. Related Art
In order to elevate the degree of integration of a semiconductor apparatus, a three-dimensional semiconductor apparatus has been developed in which a plurality of chips are stacked and packaged. Since two or more chips are vertically stacked, the 3D semiconductor apparatus can achieve a maximum degree of integration in the same space.
Various schemes exist to realize the three-dimensional semiconductor apparatus. In one scheme, a plurality of chips with the same structure are stacked and the stacked chips are coupled to one another using wires, such as metal lines, so that they operate as a single semiconductor apparatus.
Also, recently, a through-silicon via (TSV) type semiconductor apparatus has been disclosed in the art, in which silicon vias are formed through a plurality of stacked chips so that all the chips are electrically connected to one another. In the TSV type semiconductor apparatus, since the chips are electrically connected to one another through the silicon vias vertically passing through the chips, it is possible to efficiently reduce the area of the package, as compared with a semiconductor apparatus in which respective chips are electrically connected to one another through bonding wirings bonded adjacent to the edges of the chips.
The number of TSVs for connecting the plurality of chips gradually increases. Therefore, in step with the increase in the number of TSVs, a technology for replacing defective TSVs with normal TSVs is needed. This can be accomplished using fuse information, such as a fuse circuit for storing information as to whether TSVs are normal or defective. In the case where the fuse circuit is disposed in each of the stacked chips, while the problem of replacing defective TSVs can be solved, an inefficiency may result in terms of the chip area.